Computing Classification System 1998

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C.1 PROCESSOR ARCHITECTURES ( 0 Dok. )

  • C.1.0 General ( 0 Dok. )

  • C.1.1 Single Data Stream Architectures ( 0 Dok. )
    • C.1.1 Multiple-instruction-stream, single-data-stream processors (MISD)**
    • C.1.1 Pipeline processors**
    • C.1.1 RISC/CISC, VLIW architectures (NEW)
    • C.1.1 Single-instruction-stream, single-data-stream processors (SISD)**
    • C.1.1 Von Neumann architectures**

  • C.1.2 Multiple Data Stream Architectures (Multiprocessors) ( 0 Dok. )
    • C.1.2 Array and vector processors
    • C.1.2 Associative processors
    • C.1.2 Connection machines
    • C.1.2 Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)
    • C.1.2 Multiple-instruction-stream, multiple-data-stream processors (MIMD)
    • C.1.2 Parallel processors**
    • C.1.2 Pipeline processors**
    • C.1.2 Single-instruction-stream, multiple-data-stream processors (SIMD)

  • C.1.3 Other Architecture Styles ( 0 Dok. )
    • C.1.3 Adaptable architectures
    • C.1.3 Analog computers (NEW)
    • C.1.3 Capability architectures**
    • C.1.3 Cellular architecture (e.g., mobile) (REVISED)
    • C.1.3 Data-flow architectures
    • C.1.3 Heterogeneous (hybrid) systems (NEW)
    • C.1.3 High-level language architectures**
    • C.1.3 Neural nets
    • C.1.3 Pipeline processors (NEW)
    • C.1.3 Stack-oriented processors**

  • C.1.4 Parallel Architectures (NEW) ( 0 Dok. )
    • C.1.4 Distributed architectures (NEW)
    • C.1.4 Mobile processors (NEW)

  • C.1.m Miscellaneous ( 0 Dok. )
    • C.1.m Analog computers**
    • C.1.m Hybrid systems**


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